ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 79

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
14.3.1 HcRhDescriptorA register (R/W: 12h/92h)
14.3 HC root hub registers
R/W
15
7
0
-
-
Table 55.
All registers included in this partition are dedicated to the USB root hub, which is an
integral part of the host controller although it is functionally a separate entity. The HCD
emulates USB Driver (USBD) accesses to the root hub by using a register interface. The
HCD maintains many USB-defined hub features that are not required to be supported in
the hardware. For example, the hub’s device, configuration, interface and endpoint
descriptors are maintained only in the HCD, as well as some static fields of the class
descriptor. The HCD also maintains and decodes the address of the root hub device and
other trivial operations that are better suited to the software than to the hardware.
Root hub registers are developed to maintain the similarity of bit organization and
operation to typical hubs found in the system.
Four registers are defined as follows:
Each register is read and written as a double word. These registers are only written during
initialization to correspond with the system implementation. The HcRhDescriptorA and
HcRhDescriptorB registers can be read or written, regardless of the USB states of the
host controller. You can write to HcRhStatus and HcRhPortStatus only when the host
controller is in the USBOperational state.
The HcRhDescriptorA register is the first of two registers describing the characteristics of
the root hub. The bit allocation is given in
Code (Hex): 12 — read
Bit
31 to 11
10 to 0
•
•
•
•
HcRhDescriptorA
HcRhDescriptorB
HcRhStatus
HcRhPortStatus[1:NDP]
R/W
14
6
0
-
-
Symbol
-
LST[10:0]
HcLSThreshold register: bit description
reserved
R/W
13
5
1
-
-
Rev. 07 — 29 September 2009
Description
reserved
LSThreshold: Contains a value that is compared to the FrameRemaining
(FR) field before a low-speed transaction is initiated. The transaction is
started only if FrameRemaining (FR) ≥ this field. The value is calculated by
the HCD. The HCD must consider transmission and set-up overhead, while
calculating this value.
R/W
12
4
0
-
-
LST[7:0]
Table
R/W
11
3
1
-
-
56.
Single-chip USB OTG controller
R/W
R/W
10
1
2
0
LST[10:8]
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
9
1
1
0
ISP1362
R/W
R/W
79 of 147
8
0
0
0