ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 116

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

Table 128. DcEndpointStatusImage register: bit allocation
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
15.2.5 Clear endpoint buffer (70h, 72h to 7Fh)
15.2.6 DcEndpointStatusImage register (D0h to DFh)
EPSTAL
R
7
0
This command unlocks and clears the buffer of the selected OUT endpoint, allowing the
reception of new packets. Reception of a complete packet causes the Buffer Full flag of an
OUT endpoint to be set. Any subsequent packets are refused by returning a NAK
condition, until the buffer is unlocked using this command. For a double-buffered
endpoint, this command switches the current buffer memory for CPU access.
Remark: For special aspects of the control OUT endpoint, see
Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoints 1 to 14)
Transaction — none (code only)
This command is used to check the status of the selected endpoint buffer memory, without
clearing any status or interrupt bits. The command accesses the DcEndpointStatusImage
register, which contains a copy of the DcEndpointStatus register. The bit allocation of the
DcEndpointStatusImage register is shown in
Code (Hex): D0 to DF — check status (control OUT, control IN, endpoints 1 to 14)
Transaction — write or read 1 byte (code or data)
Table 129. DcEndpointStatusImage register: bit description
Bit
7
6
5
4
3
2
1
0
EPFULL1
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVERWRITE
SETUPT
CPUBUF
-
R
6
0
EPFULL0
R
5
0
Rev. 07 — 29 September 2009
Description
This bit indicates whether the endpoint is stalled or not (1 = stalled; 0 =
not stalled).
Logic 1 indicates that the secondary endpoint buffer is full.
Logic 1 indicates that the primary endpoint buffer is full.
This bit indicates data PID of the next packet (0 = DATA0 PID; 1 =
DATA1 PID).
This bit is set by the hardware. Logic 1 indicates that a new set-up
packet has overwritten the previous set-up information, before it was
acknowledged or before the endpoint was stalled. Once writing of the
set-up data is completed, a read back of this register clears this bit.
The firmware must check this bit before sending an acknowledge set-up
command or stalling the endpoint. On reading logic 1, the firmware must
stop ongoing set-up actions and wait for a new set-up packet.
Logic 1 indicates that the buffer contains a set-up packet.
This bit indicates which buffer is currently selected for CPU access (0 =
primary buffer; 1 = secondary buffer).
reserved
DATA_PID
R
4
0
WRITE
OVER
Table
R
3
0
128.
SETUPT
Single-chip USB OTG controller
R
2
0
Section
CPUBUF
© ST-ERICSSON 2009. All rights reserved.
R
1
0
12.3.6.
ISP1362
reserved
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0
-
-