ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 103

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

Table 103. HcATLCurrentActivePTD register: bit allocation
Table 105. HcATLPTDDoneThresholdCount register: bit allocation
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
14.9.8 HcATLPTDDoneThresholdCount register (R/W: 51h/D1h)
15
15
7
7
-
-
-
-
-
-
-
-
Table 104. HcATLCurrentActivePTD register: bit description
This register specifies the number of ATL PTDs to be done to trigger an ATL interrupt. If
set to 08h, the host controller will trigger the ATL interrupt (in the HcμPInterrupt register)
once every eight ATL PTDs are done.
Remark: Do not write 0000h to this register.
Code (Hex): 51 — read
Code (Hex): D1 — write
Table 106. HcATLPTDDoneThresholdCount register: bit description
Bit
15 to 5
4 to 0
Bit
15 to 5 -
4 to 0
reserved
reserved
14
14
6
6
-
-
-
-
-
-
-
-
Symbol
PTDDoneCount
[4:0]
Symbol
-
ActivePTD[4:0]
13
13
5
5
-
-
-
-
-
-
-
-
Rev. 07 — 29 September 2009
Description
reserved
Number of PTDs to be processed by the host controller to generate an
ATL interrupt.
Description
reserved
This 5-bit number represents the PTD that is currently active.
R/W
12
12
R
4
0
4
0
-
-
-
-
reserved
reserved
Table 105
R/W
11
11
R
3
0
3
0
-
-
-
-
shows the bit allocation of the register.
PTDDoneCount[4:0]
ActivePTD[4:0]
Single-chip USB OTG controller
R/W
10
10
R
2
0
2
0
-
-
-
-
© ST-ERICSSON 2009. All rights reserved.
R/W
R
9
1
0
9
1
0
-
-
-
-
ISP1362
103 of 147
R/W
R
8
0
0
8
0
1
-
-
-
-