ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 117

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

Table 130. DcErrorCode register: bit allocation
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
15.2.7 Acknowledge set up (F4h)
15.3.1 Read endpoint error code (R: A0h to AFh)
UNREAD
15.3 General commands
R
7
0
This command acknowledges to the host that a set-up packet is received. The arrival of a
set-up packet disables the Validate Buffer and Clear Buffer commands for the control IN
and OUT endpoints. The microprocessor must re-enable these commands by sending an
acknowledge set-up command, see
Code (Hex): F4 — acknowledge set up
Transaction — none (code only)
This command returns the status of the last transaction of the selected endpoint, as stored
in the DcErrorCode register. Each new transaction overwrites the previous status
information. The bit allocation of the DcErrorCode register is shown in
Code (Hex): A0 to AF — read error code (control OUT, control IN, endpoints 1 to 14)
Transaction — read 1 byte (code or data)
Table 131. DcErrorCode register: bit description
Table 132. Transaction error codes
Bit
7
6
5
4 to 1 ERROR[3:0] Error code. For error description, see
0
Error code
(Binary)
0000
0001
0010
0011
0100
0101
0110
0111
DATA01
Symbol
UNREAD
DATA01
-
RTOK
R
6
0
Description
no error
PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0
PID unknown; encoding is valid, but PID does not exist
unexpected packet; packet is not of the expected type (token, data or
acknowledge) or is a set-up token to a non-control endpoint
token CRC error
data CRC error
time-out error
babble error
reserved
5
-
-
Description
Logic 1 indicates that a new event occurred before the previous status is
read.
This bit indicates the PID type of the last successfully received or
transmitted packet (0 = DATA0 PID; 1 = DATA1 PID).
reserved
Logic 1 indicates that data was successfully received or transmitted.
Rev. 07 — 29 September 2009
R
4
0
Section
12.3.6.
R
3
0
ERROR[3:0]
Table
Single-chip USB OTG controller
R
2
0
132.
© ST-ERICSSON 2009. All rights reserved.
R
1
0
Table
ISP1362
130.
RTOK
117 of 147
R
0
0