ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 144

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

26. Contents
1
2
3
3.1
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
8.1
8.1.1
8.1.2
8.2
8.3
8.4
8.5
8.5.1
8.5.2
8.6
8.6.1
8.6.2
8.7
8.7.1
8.7.2
8.7.3
8.7.4
8.7.4.1
8.7.4.2
ISP1362_7
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . 12
Host and device bus interface . . . . . . . . . . . . 13
Host/peripheral roles . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
On-The-Go (OTG) controller. . . . . . . . . . . . . . 12
Advanced ST-Ericsson slave host controller . 12
ST-Ericsson peripheral controller . . . . . . . . . . 12
Phase-Locked Loop (PLL) clock multiplier . . . 12
USB and OTG transceivers . . . . . . . . . . . . . . 12
Overcurrent protection . . . . . . . . . . . . . . . . . . 12
Bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Peripheral controller and host controller buffer
memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory organization . . . . . . . . . . . . . . . . . . . 14
Memory organization for the host controller . . 14
Memory organization for the peripheral
controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PIO access mode . . . . . . . . . . . . . . . . . . . . . . 18
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PIO access to internal control registers . . . . . 20
PIO access to the buffer memory . . . . . . . . . . 23
PIO access to the buffer memory by using direct
addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PIO access to the buffer memory by using indirect
addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Setting up a DMA transfer . . . . . . . . . . . . . . . 25
Configuring registers for a DMA transfer . . . . 25
Combining the two DMA channels . . . . . . . . . 26
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Interrupt in the host controller and the OTG
controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Interrupt in the peripheral controller . . . . . . . . 28
Combining INT1 and INT2 . . . . . . . . . . . . . . . 29
Behavior difference between level-triggered and
edge-triggered interrupts . . . . . . . . . . . . . . . . 29
Level-triggered interrupt . . . . . . . . . . . . . . . . . 29
Edge-triggered interrupt . . . . . . . . . . . . . . . . . 29
Rev. 07 — 29 September 2009
9
10
10.1
10.2
10.3
10.3.1
10.3.2
10.4
10.4.1
10.4.2
10.4.3
10.5
10.6
11
11.1
11.2
11.3
11.4
11.5
11.5.1
11.5.1.1
11.5.1.2
11.5.1.3
11.5.1.4
11.5.1.5
11.6
11.7
11.8
11.8.1
11.8.2
11.8.3
11.8.4
11.9
12
12.1
12.1.1
12.1.2
12.2
12.2.1
12.2.2
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 30
On-The-Go (OTG) controller. . . . . . . . . . . . . . 31
USB Host Controller (HC). . . . . . . . . . . . . . . . 38
USB peripheral controller. . . . . . . . . . . . . . . . 49
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Dual-role device . . . . . . . . . . . . . . . . . . . . . . . 31
Session Request Protocol (SRP). . . . . . . . . . 32
B-device initiating SRP . . . . . . . . . . . . . . . . . 32
A-device responding to SRP . . . . . . . . . . . . . 32
Host Negotiation Protocol (HNP) . . . . . . . . . . 33
Sequence of HNP events. . . . . . . . . . . . . . . . 33
OTG state diagrams. . . . . . . . . . . . . . . . . . . . 34
HNP implementation and OTG state machine 36
Power saving in the idle state and during
wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Current capacity of the OTG charge pump . . 37
USB states of the host controller . . . . . . . . . . 38
USB traffic generation . . . . . . . . . . . . . . . . . . 39
USB ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Proprietary Transfer Descriptor (PTD) . . . . . . 40
Features of the control and bulk transfer
(aperiodic transfer). . . . . . . . . . . . . . . . . . . . . 44
Sending a USB device request (Get
Descriptor) . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Step 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Step 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Step 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Step 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Step 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Features of the interrupt transfer . . . . . . . . . . 45
Features of the Isochronous (ISO) transfer . . 45
Overcurrent protection circuit. . . . . . . . . . . . . 46
Using internal overcurrent detection circuit . . 46
Using external overcurrent detection circuit. . 47
Overcurrent detection circuit using internal charge
pump in OTG mode . . . . . . . . . . . . . . . . . . . . 47
Overcurrent detection circuit using external 5 V
power source in OTG mode. . . . . . . . . . . . . . 48
ISP1362 host controller power management. 48
Peripheral controller data transfer operation . 49
IN data transfer . . . . . . . . . . . . . . . . . . . . . . . 49
OUT data transfer . . . . . . . . . . . . . . . . . . . . . 49
Device DMA transfer . . . . . . . . . . . . . . . . . . . 50
DMA for an IN endpoint (internal peripheral
controller to the external USB host) . . . . . . . . 50
DMA for an OUT endpoint (external USB host to
internal peripheral controller) . . . . . . . . . . . . . 50
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
ISP1362
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