ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 15

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
The INTL and ATL buffers use ‘blocked memory management’ scheme to enhance the
status and control capability of each and every individual Proprietary Transfer Descriptor
(PTD) structure. The INTL and ATL buffers are further divided into blocks of equal sizes,
depending on the value written to the HcATLBlkSize register (ATL) and the
HcINTLBlkSize register (INTL). The ISP1362 host controller supports up to 32 blocks in
the ATL and INTL buffers. Each of these blocks can be used for one complete PTD data.
Note that the block size does not include the 8 bytes PTD header and is strictly the size of
the payload. Both the ATL and INTL block sizes must be a multiple of double word
(4 bytes).
Fig 4.
Recommended values of the ISP1362 buffer memory allocation
Rev. 07 — 29 September 2009
0FFFh
07FFh
0A00h
03FFh
09FFh
0000h
0800h
0400h
ATL area (1536 bytes)
ISTL0 area (512 bytes)
ISTL1 area (512 bytes)
INTL area (512 bytes)
004aaa053
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
ISP1362
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