ADSP-BF592KCPZ Analog Devices Inc, ADSP-BF592KCPZ Datasheet - Page 6

• Manufacturer Part Number: ADSP-BF592KCPZ
• Description: 58T4522
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF592KCPZ

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Rohs Compliant: YES
• Frequency: 400MHz
• Embedded Interface Type: PPI, SPI, UART
• No. Of I/o's: 32
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Core Supply Voltage: 1.4V
• Lead Free Status / RoHS Status: Compliant

ADSP-BF592
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The processor event controller consists of two stages: the core
event controller (CEC) and the system interrupt controller
(SIC). The core event controller works with the system interrupt
controller to prioritize and control all system events. Conceptu-
ally, interrupts from the peripherals enter into the SIC and are
then routed directly into the general-purpose interrupts of the
CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the processor. The inputs to
the CEC, their names in the event vector table (EVT), and their
priorities are described in the ADSP-BF59x Blackfin Processor
Hardware Reference, “System Interrupts” chapter.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout-
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processor provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writ-
ing the appropriate values into the interrupt assignment
registers (SIC_IARx). The inputs into the SIC and the default
mappings into the CEC are described in the ADSP-BF59x Black-
fin Processor Hardware Reference, “System Interrupts” chapter.
The SIC allows further control of event processing by providing
three pairs of 32-bit interrupt control and status registers. Each
register contains a bit, corresponding to each peripheral inter-
rupt event. For more information, see the ADSP-BF59x Blackfin
Processor Hardware Reference, “System Interrupts” chapter.
DMA CONTROLLERS
The processor has multiple, independent DMA channels that
support automated data transfers with minimal overhead for
the processor core. DMA transfers can occur between the pro-
cessor’s internal memories and any of its DMA-capable
peripherals. DMA-capable peripherals include the SPORTs, SPI
ports, UART, and PPI. Each individual DMA-capable periph-
eral has at least one dedicated DMA channel.
• Exceptions – Events that occur synchronously to program
• Interrupts – Events that occur asynchronously to program
flow (in other words, the exception is taken before the
instruction is allowed to complete). Conditions such as
data alignment violations and undefined instructions cause
exceptions.
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.
Rev. A | Page 6 of 44 | August 2011
The processor DMA controller supports both one-dimensional
(1-D) and two-dimensional (2-D) DMA transfers. DMA trans-
fer initialization can be implemented from registers or from sets
of parameters called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
Examples of DMA types supported by the processor DMA con-
troller include:
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels, which are provided for transfers
between the various memories of the processor system with
minimal processor intervention. Memory DMA transfers can be
controlled by a very flexible descriptor-based methodology or
by a standard register-based autobuffer mechanism.
PROCESSOR PERIPHERALS
The ADSP-BF592 processor contains a rich set of peripherals
connected to the core via several high bandwidth buses, provid-
ing flexibility in system configuration, as well as excellent
overall system performance (see
contains dedicated communication modules and high speed
serial and parallel ports, an interrupt controller for flexible man-
agement of interrupts from the on-chip peripherals or external
sources, and power management control functions to tailor the
performance and power characteristics of the processor and sys-
tem to many application scenarios.
The SPORTs, SPIs, UART, and PPI peripherals are supported
by a flexible DMA structure. There are also separate memory
DMA channels dedicated to data transfers between the proces-
sor’s various memory spaces, including boot ROM. Multiple
on-chip buses running at up to 100 MHz provide enough band-
width to keep the processor core running along with activity on
all of the on-chip and external peripherals.
The ADSP-BF592 processor includes an interface to an off-chip
voltage regulator in support of the processor’s dynamic power
management capability.
Watchdog Timer
The processor includes a 32-bit timer that can be used to imple-
ment a software watchdog function. A software watchdog can
improve system availability by forcing the processor to a known
state through generation of a hardware reset, nonmaskable
interrupt (NMI), or general-purpose interrupt, if the timer
expires before being reset by software. The programmer
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
full or fractionally full buffer
base DMA address within a common page
Figure
1). The processor also