ADSP-BF592KCPZ Analog Devices Inc, ADSP-BF592KCPZ Datasheet - Page 11

• Manufacturer Part Number: ADSP-BF592KCPZ
• Description: 58T4522
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF592KCPZ

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Rohs Compliant: YES
• Frequency: 400MHz
• Embedded Interface Type: PPI, SPI, UART
• No. Of I/o's: 32
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Core Supply Voltage: 1.4V
• Lead Free Status / RoHS Status: Compliant

BOOTING MODES
The processor has several mechanisms (listed in
automatically loading internal and external memory after a
reset. The boot mode is defined by the BMODE input pins dedi-
cated to this purpose. There are two categories of boot modes.
In master boot modes, the processor actively loads data from
parallel or serial memories. In slave boot modes, the processor
receives data from external host devices.
Table 6. Booting Modes
The boot modes listed in
nisms for automatically loading the processor’s internal and
external memories after a reset. By default, all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time.
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple-
ment the modes shown in
BMODE2–0 Description
000
001
010
011
100
101
110
111
• IDLE State/No Boot (BMODE - 0x0) — In this mode, the
• SPI1 master boot from flash (BMODE = 0x2) — In this
• SPI1 slave boot from external master (BMODE = 0x3) — In
boot kernel transitions the processor into Idle state. The
processor can then be controlled through JTAG for recov-
ery, debug, or other functions.
mode, SPI1 is configured to operate in master mode and to
connect to 8-, 16-, 24-, or 32-bit addressable devices. The
processor uses the PG11/SPI1_SSEL5 to select a single SPI
EEPROM/flash device, submits a read command and suc-
cessive address bytes (0×00) until a valid 8-, 16-, 24-, or 32-
bit addressable device is detected, and begins clocking data
into the processor. Pull-up resistors are required on the
SSEL and MISO pins. By default, a value of 0×85 is written
to the SPI_BAUD register.
this mode, SPI1 is configured to operate in slave mode and
to receive the bytes of the .LDR file from a SPI host (mas-
ter) agent. To hold off the host device from transmitting
while the boot ROM is busy, the Blackfin processor asserts
a GPIO pin, called host wait (HWAIT), to signal to the host
device not to send any more bytes until the pin is deas-
serted. The host must interrogate the HWAIT signal,
available on PG4, before transmitting every data unit to the
processor. A pull-up resistor is required on the SPI1_SS
input. A pull-down on the serial clock may improve signal
quality and booting robustness.
Idle/No Boot
Reserved
SPI1 master boot from Flash, using SPI1_SSEL5 on PG11
SPI1 slave boot from external master
SPI0 master boot from Flash, using SPI0_SSEL2 on PF8
Boot from PPI port
Boot from UART host device
Execute from Internal L1 ROM
Table 6
Table
6.
provide a number of mecha-
Table
Rev. A | Page 11 of 44 | August 2011
6) for
For each of the boot modes (except Execute from internal L1
ROM), a 16 byte header is first brought in from an external
device. The header specifies the number of bytes to be trans-
ferred and the memory destination address. Multiple memory
blocks may be loaded by any boot sequence. Once all blocks are
loaded, program execution commences from the start of L1
instruction SRAM.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
latter case. Bits 7–4 in the system reset configuration (SYSCR)
register can be used to bypass the boot kernel or simulate a
wakeup-from-hibernate boot in case of a software reset.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to speed up
booting by managing the PLL, clock frequencies, or serial bit
rates.
The boot ROM also features C-callable functions that can be
called by the user application at run time. This enables second
stage boot or boot management schemes to be implemented
with ease.
• SPI0 master boot from flash (BMODE = 0x4) — In this
• Boot from PPI host device (BMODE = 0x5) — The proces-
• Boot from UART host device (BMODE = 0x6) — In this
• Execute from internal L1 ROM (BMODE = 0x7) — In this
mode SPI0 is configured to operate in master mode and to
connect to 8-, 16-, 24-, or 32-bit addressable devices. The
processor uses the PF8/SPI0_SSEL2 to select a single SPI
EEPROM/flash device, submits a read command and suc-
cessive address bytes (0×00) until a valid 8-, 16-, 24-, or 32-
bit addressable device is detected, and begins clocking data
into the processor. Pull-up resistors are required on the
SSEL and MISO pins. By default, a value of 0×85 is written
to the SPI_BAUD register.
sor operates in PPI slave mode and is configured to receive
the bytes of the LDR file from a PPI host (master) agent.
mode UART0 is used as the booting source. Using an auto-
baud handshake sequence, a boot-stream formatted
program is downloaded by the host. The host selects a bit
rate within the UART clocking capabilities. When per-
forming the autobaud, the UART expects a “@” (0×40)
character (eight bits data, one start bit, one stop bit, no par-
ity bit) on the RXD pin to determine the bit rate. The
UART then replies with an acknowledgment which is com-
posed of 4 bytes (0xBF—the value of UART_DLL) and
(0×00—the value of UART_DLH). The host can then
download the boot stream. To hold off the host the proces-
sor signals the host with the boot host wait (HWAIT)
signal. Therefore, the host must monitor the HWAIT, (on
PG4), before every transmitted byte.
mode the processor begins execution from the on-chip 64k
byte L1 instruction ROM starting at address 0xFFA1 0000.
ADSP-BF592