ADSP-BF592KCPZ Analog Devices Inc, ADSP-BF592KCPZ Datasheet - Page 23

• Manufacturer Part Number: ADSP-BF592KCPZ
• Description: 58T4522
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF592KCPZ

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Rohs Compliant: YES
• Frequency: 400MHz
• Embedded Interface Type: PPI, SPI, UART
• No. Of I/o's: 32
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Core Supply Voltage: 1.4V
• Lead Free Status / RoHS Status: Compliant

Parallel Peripheral Interface Timing
Table 20
peripheral interface operations.
Table 20. Parallel Peripheral Interface Timing
1
2
Parameter
Timing Requirements
t
t
Timing Requirements—GP Input and Frame Capture Modes
t
t
t
t
t
Switching Characteristics—GP Output and Frame Capture Modes
t
t
t
t
PPI_CLK frequency cannot exceed f
The PPI port is fully enabled 4 PPI clock cycles after the PAB write to the PPI port enable bit. Only after the PPI port is fully enabled are external frame syncs and data words
PCLKW
PCLK
PSUD
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
guaranteed to be received correctly by the PPI peripheral.
and
Figure 9
PPI_CLK Width
PPI_CLK Period
External Frame Sync Startup Delay
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
PPI_FS1/2
PPI_DATA
PPI_CLK
PPI_FS1/2
PPI_CLK
through
1
SCLK
1
t
SFSPE
Figure 13
/2
FRAME SYNC SAMPLED
DATA SAMPLED /
describe parallel
Figure 10. PPI GP Rx Mode with External Frame Sync Timing
2
Figure 9. PPI with External Frame Sync Timing
Rev. A | Page 23 of 44 | August 2011
t
HFSPE
t
SDRPE
FRAME SYNC SAMPLED
DATA SAMPLED /
t
PSUD
Min
t
2 × t
4 × t
6.7
1.8
4.1
2
1.7
2.3
SCLK
t
PCLKW
–1.5
SCLK
PCLK
t
HDRPE
V
–1.5
DDEXT
= 1.8 V
9.0
8.7
Max
t
PCLK
Min
t
2 × t
4 × t
6.7
1.6
3.5
1.6
1.7
1.9
SCLK
–1.5
SCLK
PCLK
V
DDEXT
–1.5
= 2.5 V/3.3 V
ADSP-BF592
Max
8.0
8.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns