CYII5SC1300AB-QWC Cypress Semiconductor Corp, CYII5SC1300AB-QWC Datasheet - Page 9

• Manufacturer Part Number: CYII5SC1300AB-QWC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYII5SC1300AB-QWC

• Lead Free Status / RoHS Status: Not Compliant

Image Core Operation
Image Core Operation and Signalling
Figure 8
sub-sampling and column/row swapping circuits. Most of the
signals involved are not available from the outside because they
are generated by the X-sequencer and SS-sequencer blocks.
The integration of the pixels is controlled by internal signals such
as reset, sample, and hold which are generated by the on-chip
SS-sequencer that is controlled with the external signals
SS_START and SS_STOP. Reading out the pixel array starts
by applying a Y_START together with a Y_CLOCK signal; inter-
nally this is followed by a calibration sequence to calibrate the
output amplifiers (during the row blanking time). Signals
necessary to do this calibration are generated by the on-chip
X-sequencer. This calibration sequence takes typically 3.5 μs
and is necessary to remove ‘Fixed Pattern Noise’ of the pixels
and of the column amplifiers themselves by means of a double
sampling technique. After the row blanking time, the pixels are
fed to the output amplifier. The pixel rate is equal to the
SYS_CLOCK frequency.
Document #: 38-05710 Rev. *G
is a functional representation of the image core without
VDDR_LEFT
SYS_CLOCK
Y_CLOCK
Y_START
VDDH
Y-left addressing
BUS_A
BUS_B
Read-pointer
Pixel column
Figure 8. Image Core
X addressing
Pixel
SAMPLE
A
RESET
HOLD
Pixel
Image Core Supply Considerations
The image sensor has several supply voltages:
VDDH is the voltage that controls the sample switches. Do not
apply a higher voltage than this to the chip.
The VDDR_LEFT voltage is the highest (nominal) reset voltage
of the pixel core.
The VDDR_RIGHT voltage is generated from the VDDR_LEFT
voltage using a circuit that is programmed with the
KNEEPOINT_LSB/MSB bits in the sequencer register (see also
“Pixel reset knee-point for multiple slope operation (bits 8, 9, and
10).”
from the circuit and apply an external voltage to supply the
multiple slope reset voltage by setting the VDDR_RIGHT_EXT
bit in the SEQUENCER register. When no external voltage is
applied (recommended), connect the VDDR_RIGHT pin to a
capacitor (recommended value = 1µF). VDDC is the pixel core
supply. VDDA is the image core and periphery analog supply.
VDDD is the image core and periphery digital supply.
Note that the IBIS5-B-1300 image sensor has no on-chip power
rejection circuitry. As a consequence all variations on the analog
supply voltages can contribute to random variations (noise) on
the analog pixel signal, which is seen as random noise in the
image. During the camera design, take precautions to supply the
sensor with very stable supply voltages to avoid this additional
noise. The pixel array (VDDR_LEFT, VDDH and VDDC) analog
supplies are especially vulnerable to this.
B
Pixel row
on page 17). You can disconnect the VDDR_RIGHT pin
Column amplifiers
Output amplifier
Y-right addressing
Y_START
Y_CLOCK
PXL_OUT
Vddreset
VDDR_RIGHT
VDDC
CYII5SM1300AB
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