CYII5SC1300AB-QWC Cypress Semiconductor Corp, CYII5SC1300AB-QWC Datasheet - Page 18

• Manufacturer Part Number: CYII5SC1300AB-QWC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYII5SC1300AB-QWC

• Lead Free Status / RoHS Status: Not Compliant

Table 18. Multiple Slope Register Settings
NROF_PIXELS Register (11:0)
After the internal x_sync is generated (start of the pixel readout
of a particular row), the PIXEL_VALID signal goes high. The
PIXEL_VALID signal goes low when the pixel counter reaches
the value loaded in the NROF_PIXEL register. Due to the fact
that two pixels are read at the same clock cycle, you must divide
this number by 2 (NROF_PIXELS = (width of ROI / 2) – 1).
Document #: 38-05710 Rev. *G
6. External Pixel Reset Voltage for Multiple Slope (bit 11)
In normal (single slope) mode the pixel reset is controlled from
the left side of the image core using the voltage applied on pin
VDDR_LEFT as pixel reset voltage.
In multiple slope operation, apply one or more variable pixel
reset voltages.
Bits KNEE_POINT_MSB and KNEE_POINT_LSB select the
on chip-generated pixel reset voltage.
Bit KNEE_POINT_ENABLE set to ’1’ switches control to the
right side of the image core so the pixel reset voltage
(VDDR_RIGHT), selected by bits KNEE_POINT_MSB/LSB,
is used.
Use bit KNEE_POINT_ENABLE only for multiple slope oper-
ation in synchronous shutter mode. In rolling shutter mode,
use only the bits KNEE_POINT_MSB/LSB to select the sec-
ond knee-point in dual slope operation. The actual knee-point
depends on VDDH, VDDR_LEFT and VDDC applied to the
sensor.
Setting bit VDDR_RIGHT_EXT to ’1’ disables the circuit that
generates the variable pixel reset voltage and uses the volt-
age externally applied to pin VDDR_RIGHT as the dou-
ble/multiple slope reset voltage.
Setting bit VDDR_RIGHT_EXT to ’0’ allows you to monitor the
variable pixel reset voltage (used for multiple slope operation)
on pin VDDR_RIGHT.
MSB/LSB
KNEE_POINT
00
01
10
11
ENABLE
0 or 1
s h ift-r e g is te r
S y n c o f le ft
1
1
1
Figure 18. Synchronization of the Shift Registers in Rolling Shutter Mode
Pixel Reset Voltage
VDDR_LEFT – 0.76
VDDR_LEFT – 1.52
VDDR_LEFT – 2.28
(V)VDDR_RIGHT
VDDR_LEFT
L in e n
Knee-point
+ 0.76
+ 1.52
+ 2.28
S y n c o f r ig h t
s h ift-r e g is te r
(V)
0
ROF_LINES Register (11:0)
After the internal yl_sync is generated (start of the frame readout
with Y_START), the line counter increases with each Y_CLOCK
pulse until it reaches the value loaded in the NROF_LINES
register and generates a LAST_LINE pulse. It must be noted that
the value loaded in the register must be (Number of lines
required - 1).
INT_TIME Register (11:0)
Use the INT_TIME register to set the integration time of the
electronic shutter. The interpretation of the INT_TIME depends
on the chosen shutter type (rolling or synchronous).
1. Global shutter
2. Rolling shutter
After the SS_START pulse is applied an internal counter
counts the number of SS granulated clock cycles until it
reaches the value loaded in the INT_TIME register and gen-
erates a TIME_OUT pulse. Use this TIME_OUT pulse to gen-
erate the SS_STOP pulse to stop the integration. When the
INT_TIME register is used, the maximum integration time is:
TINT_MAX = 212 * 256 (maximum granularity) * (40 MHZ) – 1
= 26.2 ms.
You can increase this maximum time if you use an external
counter to trigger SS_STOP. Ten is the minimal value that you
can load into the INT_TIME register (see also
granularities (bits 4, 5, 6 and 7).”
When the Y_START pulse is applied (start of the frame read-
out), the sequencer generates the yl_sync pulse for the left
Y-shift register (read out Y-shift register). This loads the left
Y-shift register with the pointer loaded in YL_REG register. At
each Y_CLOCK pulse, the pointer shifts to the next row and
the integration time counter increases until it reaches the val-
ue loaded in the INT_TIME register. At that moment, the se-
quencer generates the yr_sync pulse for the right Y-shift reg-
ister; it loads the right Y-shift register (reset Y-shift register)
with the pointer loaded in YR_REG register (see
The integration time counter is reset when the sync for the left
Y-shift register, yl_sync is asserted. Both shift registers keep
moving until the next sync is asserted, i.e., the yl_sync for the
left Y-shift register (generated by Y_START) and the yr_sync
for the right Y-shift register (generated when the integration
time counter reaches the INT_TIME value)..
Treg_int Difference between the left and right pointer = value
set in the INT_TIME register (number of lines).
T
re g _ in t
S y n c
L a s t lin e , fo llo w e d b y
s y n c o f le ft s h ift- re g is te r
CYII5SM1300AB
on page 17).
T
in t
“Internal clock
Page 18 of 34
Figure
18).