CYII5SC1300AB-QWC Cypress Semiconductor Corp, CYII5SC1300AB-QWC Datasheet - Page 17

• Manufacturer Part Number: CYII5SC1300AB-QWC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYII5SC1300AB-QWC

• Lead Free Status / RoHS Status: Not Compliant

Table 15. Internal Registers (continued)
Detailed Description of the Internal Registers
Sequencer register (7:0)
Document #: 38-05710 Rev. *G
Note
1. Shutter type (bit 0).
2. Output amplifier calibration (bits 1 and 2).
3. Continuous charge (bit 3).
4. Internal clock granularities (bits 4, 5, 6 and 7).
7. Using a SYS_CLOCK of 40 MHz (25 ns period).
10 (1010)
11 (1011)
12 (1100)
13 (1101)
14 (1110)
15 (1111)
9 (1001)
The IBIS5-B-1300 image sensor has two shutter types:
0 = synchronous shutter.
1 = rolling shutter.
Bits FRAME_CAL_MODE and LINE_CAL_MODE define the
calibration mode of the output amplifier.
During every row-blanking period, a calibration is done of the
output amplifier. There are two calibration modes. The FAST
mode (= 0) forces a calibration in one cycle but is not so ac-
curate and suffers from KTC noise. The SLOW mode (= 1)
only makes incremental adjustments and is noise free.
Approximately 200 or more ’slow’ calibrations have the same
effect as one ’fast’ calibration.
Different calibration modes are set at the beginning of the
frame (FRAME_CAL_MODE bit) and for every subsequent
line that is read (LINE_CAL_MODE bit). The Y_START input
defines the beginning of a frame, Y_CLOCK defines the be-
ginning of a new row.
Some applications may require the use continuous charging
of the pixel columns instead of a pre-charge on every line
sample operation.
Setting bit CONT_CHARGE to ’1’ activates this function. The
resistor connected to pin PC_CMD controls the current level
on every pixel column.
The system clock is divided several times on-chip.
Half the system clock rate clocks the X-shift-register that con-
trols the column/pixel readout. Odd and even pixel columns
are switched to two separate buses. In the output amplifier the
Register
Bit
6:0
6:0
2:0
0
1
2
DACRAW_REG
DACFINE_REG
ADC register
TRISTATE_OUT
GAMMA
BIT_INV
Reserved
Reserved
Reserved
Reserved
Name
Amplifier DAC raw offset
Default value <6:0>: ’1000000’
Amplifier DAC fine offset
Default value <6:0>: ’1000000’
Default value <2:0>: ’011’
0 = Output bus in tri-state
0 = Gamma-correction on
1 = Bit inversion on output bus
.
Table 16. SS Sequencer Clock Granularities
The clock that drives the X-sequencer is a multiple of 4, 8, 16, or
32 times the system clock. Clocking the X-sequencer at a slower
rate (longer row blanking time; pixel read out speed is always
equal to the SYSTEM_CLOCK) results in more signal swing for
the same light conditions.
Table 17. X Sequencer Clock Granularities
5. Pixel reset knee-point for multiple slope operation (bits 8, 9,
GRAN_SS_SEQ_MSB/
GRAN_X_SEQ_MSB/
pixel signals on the two buses are combined into one pixel
stream at the same frequency as SYS_CLOCK.
Use
GRAN_SS_SEQ_LSB (bit 6) to program the clock that drives
the ’snapshot’ or synchronous shutter sequencer.
This way the integration time in synchronous shutter mode is
a multiple of 32, 64, 128, or 256 times the system clock period.
To overcome global reset issues, use the longest SS granu-
larity (bits 6 and 7 set to '1').
and 10).
the
LSB
LSB
00
01
10
00
01
10
11
11
bits
Description
GRAN_SS_SEQ_MSB
128 x SYS_CLOCK
256 x SYS_CLOCK
16 x SYS_CLOCK
32 x SYS_CLOCK
32 x SYS_CLOCK
64 x SYS_CLOCK
4 x SYS_CLOCK
8 x SYS_CLOCK
SS-Sequencer
X-Sequencer
Clock
Clock
CYII5SM1300AB
Row Blanking
(bit
Time Step
Page 17 of 34
Integration
Time
800 ns
1.6 μs
3.2 μs
6.4 μs
3.5 μs
14 μs
28 μs
7 μs
7)
[7]
and
[7]