CYII5SC1300AB-QWC Cypress Semiconductor Corp, CYII5SC1300AB-QWC Datasheet - Page 24

• Manufacturer Part Number: CYII5SC1300AB-QWC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYII5SC1300AB-QWC

• Lead Free Status / RoHS Status: Not Compliant

Rolling Shutter Operation
The integration of the light in the image sensor is done during
readout of the other lines.
The only difference with synchronous shutter is that the
TIME_OUT pin is used to indicate when the Y_SYNC pulse for
the right Y-shift-register (reset Y-shift register) is generated. This
loads the right Y-shift-register with the pointer loaded in register
YR_REG. The Y_SYNC pulse for the left Y-shift register (read
Y-shift register) is generated with Y_START.
Windowing in X-direction
An X_LOAD pulse overrides the internal X_SYNC signal, loading
a new X-pointer (stored in the X_REG register) into the
X-shift-register.
The X_LOAD pulse has to appear on the falling edge of
SYS_CLOCK and has to remain high for two SYS_CLOCK
cycles overlapping two rising edges of SYS_CLOCK. The new
X-pointer is loaded on one of the two rising edges of
SYS_CLOCK.
The available time to upload the register is T
from the previous register load to the rising edge of X_LOAD. It
depends on the settling time of the register and the X-decoder.
Document #: 38-05710 Rev. *G
Figure 27. Windowing in the X-Direction
Figure 26. Rolling Shutter Operation
load
; it is defined
The INT_TIME register defines how many lines to count before
the Y_SYNC of the right Y-shift-register is generated, hence
defining the integration time. See also
on page 18 for a detailed description of the rolling shutter
operation.
T
register(INT_TIME)
Note For normal operation the values of the YL_REG and
YR_REG registers are equal.
Table 25. T
The actual time to load the register itself depends on the
interface mode that is used.
The parallel interface is the fastest.
Parallel interface
Serial 3 Wire
int
Interface Mode
Integration time [# lines] = register(NROF_LINES) –
load
for Different Interfaces
T
load
16
1
(µs)
(about 40 SYS_CLOCK cycles)
(at 2.5 MHz data rate)
CYII5SM1300AB
INT_TIME Register (11:0)
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