CYII5SC1300AB-QWC Cypress Semiconductor Corp, CYII5SC1300AB-QWC Datasheet - Page 5

• Manufacturer Part Number: CYII5SC1300AB-QWC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYII5SC1300AB-QWC

• Lead Free Status / RoHS Status: Not Compliant

Architecture and Operation
This section presents detailed information about the most important sensor blocks
Floor Plan
Figure 2
sensor. It consists basically of a pixel array, one X- and two
Y-addressing registers for the readout in X- and Y-direction,
column amplifiers that correct for the fixed pattern noise, an
analog multiplexer, and an analog output amplifier.
Use the left Y-addressing register for readout operation. Use the
right Y-addressing register for reset of pixel rows. In multiple
slope synchronous shutter mode, the right Y-addressing register
resets the whole pixel core with a lowered reset voltage. In rolling
curtain shutter mode, use the right Y-addressing register for the
Document #: 38-05710 Rev. *G
shows the architecture of the IBIS5-B-1300 image
addressing
Y-left
Figure 2. Block Diagram of IBIS5-B-1300 Image Sensor
Pixel
Column amplifiers
X-addressing
Analog multiplexer
Pixel core
Imager core
Y-right
addressing
Output
amplifier
reset pointer in single and double slope operation to reset one
pixel row.
The on-chip sequencer generates most of the signals for the
image core. Some basic signals (like start/stop integration, line
and frame sync signals, and others.) are generated externally.
A 10-bit ADC is implemented on chip but electrically isolated
from the image core. You must route the analog pixel output to
the analog ADC input on the outside.
ADC
Sequencer
Sensor
System clock
40 MHz
External
connection
Sample
Reset
C
Column output
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