CYII5SC1300AB-QWC Cypress Semiconductor Corp, CYII5SC1300AB-QWC Datasheet - Page 12

• Manufacturer Part Number: CYII5SC1300AB-QWC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYII5SC1300AB-QWC

• Lead Free Status / RoHS Status: Not Compliant

Output Amplifier
Architecture and Settings
The output amplifier stage is user programmable for gain and
offset level. Gain is controlled by 4-bit wide word; offset by a 7-bit
wide word. Gain settings are on an exponential scale. Offset is
controlled by a 7-bit wide DAC, which selects the offset voltage
between
DAC_VLOW) on a linear scale.
The amplifier is designed to match the specifications of the
imager array output. This signal has a data rate of 40 MHz. The
output impedance of the amplifier is 260 Ohms.
At unity gain and with a mid-range offset value, the amplifier
outputs a signal in between 1.59V (light) and 2.70V (dark). This
analog range must fit to the input range of the ADC, external or
internal. The output swing in unity gain is approximately 1.11V
and it is maximum 1.78V at the highest gain settings. So, the
effective signal range is between 1.17V and 2.95V, depending
on the gain and offset settings of the amplifier.
Figure 11
and even column amplifiers sample both pixel and reset value to
perform a double sampling FPN correction. You can adjust two
different offsets using the on-chip DAC (7 bit): DAC_FINE and
DAC_RAW. DAC_FINE is used to tune the difference between
odd and even columns; DAC_RAW is used to add a common
(both even and odd columns) to the FPN corrected pixel value.
This pixel value is fed to the first amplifier stage which has an
adjustable gain, controlled by a 4-bit word (’GAIN [0…3]’).
After this, a unity feedback amplifier buffers the signal and the
signal leaves the chip. This second amplifier stage determines
the maximal readout speed, that is, the bandwidth and the slew
rate of the output signal. The whole amplifier chain is designed
for a data rate of 40 Mpix/s (@20 pF).
The analog output of the IBIS5-B-1300 image sensor is not
designed to drive very large loads on the PCB. Therefore, it is
advised that the PXL_OUT is connected to the ADC_IN right
Document #: 38-05710 Rev. *G
DAC_RAW [6:0]
odd
even
DAC_FINE [6:0]
DAC_VHIGH
DAC_VLOW
S
R
S
R
shows the architecture of the output amplifier. The odd
two
Figure 11. Output Structure
+
DAC_FINE
reference
DAC_RAW
+
voltages
GAIN [0…3]
unity gain
A
(DAC_VHIGH
1
PXL_OUT
and
below the sensor in the top layer with a thick track. It is better not
to have vias on this trace. If there is a socket being used, then it
is advised that we buffer the PXL_OUT close to the sensor
output pin and then take the signal to the ADC_IN.
Output Amplifier Gain Control
The output amplifier gain is controlled by a 4-bit word set in the
AMPLIFIER register (see section
page 19). An overview of the gain settings is given in
Table 13. Overview Gain Settings
Setting of the DAC Reference Voltage
In the output amplifier, the offset is trimmed by loading registers
DACRAW_REG and DACFINE_REG. DAC_RAW is used to
adjust the offset of the output amplifier and DAC_FINE is used
to tune the offset between the even and odd columns. These
registers are inputs for two DACs (see
the same resistor that is connected between pins DAC_VHIGH
and DAC_VLOW. The range of the DAC is defined using a
resistive division with R
The internal resistor R
The recommend resistor values for both DAC_VLOW and
DAC_VHIGH are 0Ω.
Figure 12. Internal and External ADC Connections
0000
0001
0010
0011
0100
0101
0110
0111
Bits
DAC _V HIG H = 3.3V
D A C _V LO W = 0V
DAC
DC Gain
VHIGH
1.37
1.62
1.96
2.33
2.76
3.50
4.25
5.20
has a value of approximately 7.88 kΩ.
, R
R
D A C
DAC
Amplifier Register (6:0)
CYII5SM1300AB
and R
Figure
1000
1001
1010
1011
1100
1101
1110
1111
Bits
R
7.88 kΩ
R
external
external
D A C _V H IG H
D A C _V LOW
internal
internal
VLOW.
12) that operate on
Page 12 of 34
DC Gain
11.00
11.37
11.84
12.32
12.42
6.25
7.89
9.21
Table
13.
on