CYII5SC1300AB-QWC Cypress Semiconductor Corp, CYII5SC1300AB-QWC Datasheet - Page 6

• Manufacturer Part Number: CYII5SC1300AB-QWC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYII5SC1300AB-QWC

• Lead Free Status / RoHS Status: Not Compliant

Pixel
A description of the pixel architecture and the color filter array
follows.
Architecture
The pixel architecture used in the IBIS5-B-1300 is a 4-transistor
pixel as shown in
factor technique as patented by Cypress (US patent No.
6,225,670 and others). The 4T-pixel features a snapshot shutter
but can also emulate the 3T-pixel by continuously closing
sampling switch M2. Using M2 as a global sample transistor for
all pixels enables the snapshot shutter mode. Due to this pixel
architecture, integration during read out is not possible in
synchronous shutter mode.
Document #: 38-05710 Rev. *G
Figure 3. 4T Pixel Architecture
M1
Figure
reset
sample
3. Implement the pixel using the high fill
M2
C
M3
mux
M4
Figure 5. Spectral Response for IBIS5-B-color
column
output
Color Filter Array
The IBIS5-B-1300 is also processed with a Bayer RGB color
pattern. Pixel (0,0) is a green filter and is situated on a green-blue
row. Green1 and Green2 have a slightly different spectral
response due to cross talk from neighboring pixels. Green1
pixels are located on a blue-green row, green2 pixels are located
on a green-red row.
filter array as function of the wavelength. Note that this response
curve includes the optical cross talk of the pixels.
Figure 4. Color Filter Arrangement of Pixels
Figure 5
(0,0)
G1
R
shows the response of the color
G2
CYII5SM1300AB
B
Page 6 of 34