LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 71

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 3.9
Name
ENCL_ACK/,
SEL_4
DSK_RD/,
SEL_5
DSK_WR/,
SEL_6
PARALLEL_
ESI/
D0, SEL_0
Pin Assignments for SFF-8067 Mode (Cont.)
Pin/Ball
142/E7
141/D7
140/A7
139/B7
137/E8
No.
SFF-8067 Mode
Description
When PARALLEL_ESI/ is asserted,
this is an active low acknowledge
signal sourced by the LSI53C040
back to the Fibre Channel device.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_4
signal, included for compatibility with
SFF-8045.
When PARALLEL_ESI/ is asserted,
this is an active low control signal
sourced by the drive to the
LSI53C040 to indicate the device is
ready to read data. When
PARALLEL_ESI/ is deasserted, this
signal is the SEL_5 signal, included
for compatibility with SFF-8045.
When PARALLEL_ESI/ is asserted,
this is an active low control signal
sourced by the drive to the
LSI53C040 to indicate the device is
ready to write data. When
PARALLEL_ESI/ is deasserted, this
signal is the SEL_6 signal, included
for compatibility with SFF-8045.
Used to select between the SEL_ID
and the bidirectional interface. Pull-
up resistors on the interface are 3.3
k
asserted, the drive begins the
discovery process and prepares to
read or write data. When this pin is
deasserted, the drive is presented
with SEL_ID. All SFF-8067
transactions are terminated,
regardless of the state of the
protocol.
When PARALLEL_ESI/ is asserted,
this signal contains bit 0 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_0
signal, included for compatibility with
SFF-8045.
minimum. When this pin is
8067 Port
Port 0
Port 0
Port 0
Port 0
Port 1
Pad
Configuration
4 mA open drain
bidirectional
4 mA open drain
bidirectional
4 mA open drain
bidirectional
4 mA open drain
bidirectional
4 mA open drain
bidirectional
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