LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 70

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

3.2 SFF-8067 Mode
Table 3.9
3-18
Name
D0, SEL_0
D1, SEL_1
D2, SEL_2
D3, SEL_3
Pin Assignments for SFF-8067 Mode
Pin/Ball
147/D6
146/C6
145/A6
144/B6
No.
The SFF-8067 interface is enabled when the DIFFSENS pin is tied to
V
as indicated in
Signal Descriptions
DD
. The SCSI pin functions are reassigned to SFF-8067 port functions
Description
When PARALLEL_ESI/ is asserted,
this signal contains bit 0 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_0
signal, included for compatibility with
SFF-8045.
When PARALLEL_ESI/ is asserted,
this signal contains bit 1 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_1
signal, included for compatibility with
SFF-8045.
When PARALLEL_ESI/ is asserted,
this signal contains bit 2 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_2
signal, included for compatibility with
SFF-8045.
When PARALLEL_ESI/ is asserted,
this signal contains bit 3 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_3
signal, included for compatibility with
SFF-8045.
Table
3.9.
8067 Port
Port 0
Port 0
Port 0
Port 0
Pad
Configuration
4 mA open drain
bidirectional
4 mA open drain
bidirectional
4 mA open drain
bidirectional
4 mA open drain
bidirectional