LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 68
LSI53C040-160QFP
Manufacturer Part Number
LSI53C040-160QFP
Description
Manufacturer
LSI
Datasheet
1.LSI53C040-160QFP.pdf
(212 pages)
Specifications of LSI53C040-160QFP
Mounting
Surface Mount
Lead Free Status / RoHS Status
Supplier Unconfirmed
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3.1.3 JTAG Signals
Table 3.7
3-16
Name
TCK
TMS
TDI
TDO
TRST/
JTAG Signals
Number
151
Pin
91
90
92
89
Table 3.7
Signal Descriptions
BGA Ball
Number
H10
J13
J12
J11
C5
describes the signals for the JTAG Signals group.
Description
Test Clock. The Test Clock pin
provides clocking for the JTAG test
logic and boundary scan.
Test Mode Select. The Test Mode
Select pin receives a signal to
control the JTAG test operations and
boundary scans.
Test Data In. The Test Data In pin
receives serial input data and
commands for JTAG test operations
and boundary scans.
Test Data Out. The Test Data Out pin
provides serial output data for JTAG
test operations and boundary scans.
Test Reset. The Test Reset pin
receives a signal to reset the JTAG
TAP controller. It also simulates a
power-on reset for core logic (NOTE:
not JTAG compliant).
Pad Type
5 V
tolerant
TTL input
5 V
tolerant
TTL input
5 V
tolerant
TTL input
4 mA
Output
5 V
tolerant
TTL input
Internal
Resistor
100 A
pull-up
100 A
pull-up
100 A
pull-up
None
100 A
pull-up
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