LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 202

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

multipurpose I/O bank 1 (Cont.)
multipurpose I/O bank 2
multipurpose I/O bank 3
multipurpose LED bank 0H
multipurpose LED bank 0L
multipurpose LED bank 1H
multipurpose LED bank 1L
multipurpose LED bank 2H
multipurpose LED bank 2L
O
ODR
operating conditions
output data register
P
PA[7:0] bits
parallel ESI/ value bit 5-5,
parity error bit
PCST0–PCST1 registers
pending interrupt bit 6-5,
pending interrupt not bit
PERR bit
PESI/ bit 5-5,
PHAD0–PHAD1 register
IX-4
output register
pull-down enable register
enable register
input register
latch mask register
latch register
output register
pull-down enable register
enable register
input register
latch mask register
latch register
output register
pull-down enable register
input register
latch mask register
latch register
output register
input register
latch mask register
latch register
output register
input register
latch mask register
latch register
output register
input register
latch mask register
latch register
output register
input register
latch mask register
latch register
output register
input register
latch mask register
latch register
output register
PIN bit
4-3
4-11
6-7
5-5
5-6
4-11
8-16
8-20
8-25
8-24
8-29
8-29
8-34
8-33
8-15
8-19
8-23
8-22
8-27
8-27
8-32
8-31
8-11
8-14
8-17
8-22
8-21
8-26
8-25
8-31
8-30
8-15
8-18
4-3
9-2
8-16
8-19
8-24
8-23
8-28
8-28
8-33
8-32
5-5
6-6
5-3
5-6
Index
8-14
8-17
8-20
phase match bit
physical address register
PIN bit 6-5,
PMATCH bit
PME bit
POC0 register
POC1 register
port access
port busy flag bit
port control/status register
port manual enable bit
power pins
power-on configuration one register
power-on configuration options
power-on configuration zero register
power-on options
power-on reset,
program memory
programmed I/O transfers
protocol
R
RD/ bit 5-6,
RDATA0–RDATA1 register
read data register
read interrupt bit
read register full bit
receive operations
register bits
automatic branch generation
download port select
serial ROM
serial ROM chip address
SCSI
8067 interface data nibble 5-6,
8067 port 0 interrupt 7-8, 7-14,
8067 port 1 interrupt 7-8, 7-14,
8067 read data
8067 write data
A[6:0]
AACK
AAS
AATN
ABSY
ACD
ACK 4-11, 6-6,
ACK/ 5-6,
acknowledge 4-11, 6-6,
active SCL frequency
ADB
address 0 bit
addressed as slave
AIO
AIP
AMSG
ARB
arbitrate
arbitration in progress
arbitration/selection LVD
AREQ
ARST
AS_LVD
ASEL
ASF
assert ACK/
4-4
4-8
5-3
6-3
6-8
4-5
4-7
4-8
2-3
6-3
4-5
4-5
4-5
4-4
4-4
4-8
4-8
3-17
6-6
2-25
5-7
4-7
4-6
4-11
5-7
8-4
8-5
2-22
2-23
4-4
4-11
5-4
5-4
6-8
2-3
5-3
2-13
6-7
5-3
5-3
5-4
5-3
6-8
2-23
5-5
6-3
4-4
2-8
5-3
5-3
6-7
4-6
2-22
2-21
2-21
5-7
7-15
7-15
8-5
8-4