LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 21

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.1 Functional Blocks
2.1.1 LSI53C80-Based SCSI Control Logic
2.1.2 80C32 Microcontroller Core
2.1.3 Two-Wire Serial Interface
Following are brief descriptions of the main functional blocks comprising
the LSI53C040.
The SCSI core in the LSI53C040 is based on the LSI53C80 SCSI
controller. The LSI53C80 is a first generation SCSI protocol controller
that provides simple, register-based access to SCSI control and data
signals. This core provides additional support for parity checking and a
DMA function. It supports only asynchronous SCSI transfers. It supports
both SE and LVD SCSI transfers. The LSI53C80 register set is mapped
into the Internal Features register block as shown on the memory map
in
The 80C32 microcontroller core used in the LSI53C040 is an 8-bit Intel
MCS 51 family compatible device with 256 bytes of internal scratch RAM.
This microcontroller uses a shared address/data bus and can address
either 64 Kbytes of shared program and data memory or 16 Kbytes of
internal memory and 47 Kbytes each of external program and data
memory spaces. The microcontroller executes one instruction every
12 clocks. Additional functionality includes two 16-bit timers, a full-duplex
UART, and two additional external interrupt sources (five interrupt
sources total).
The LSI53C040 has 2 Two-Wire Serial interface blocks that provide
access to external serial EEPROM storage and any other user-defined,
two-wire peripheral devices. The LSI53C040 can attempt to download
from an external serial ROM through one interface at power-on or reset.
External two-wire devices are connected to the SDA and SCL signal pins
on the LSI53C040. The Two-Wire Serial interface blocks are controlled
by a set of control registers in the Internal Features register block as
shown on the memory map in
in
Functional Blocks
Figure
Chapter
2.2. These registers are described in
6.
Figure
2.2. These registers are described
Chapter
4.
2-3