LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 107

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

ENI
STA
STO
ACK
Register: 0xFD01/0xFD03
Status Register Reads (ES0 = 1)
Read Only
PIN
RPSS
PIN
7
0
RPSS
6
0
External Interrupt Enable
Setting this bit enables the interrupt output to the
microcontroller when the PIN bit (0xFD01/0xFD03, bit 7)
is cleared (0). It causes the corresponding bit to be set in
the
interrupt is not masked in the
register.
Start
When set, this bit signifies that the byte located in the
Data register [0xFD00/0xFD02 (ES0, ES1, ES2 = 100]
will be sent out on the Two-Wire Serial bus with a start
condition as defined in the Inter-Integrated Circuit
specification.
Stop
When set, this bit signifies that a stop condition as
defined in the Inter-Integrated Circuit specification will be
sent out onto the interface.
Acknowledge
When set, this bit will enable an ACK to be transmitted
during the ninth clock cycle of the interface after receiving
a data byte.
Pending Interrupt Not
This active low bit is cleared when the Data register has
completed an operation and requires microcontroller
intervention to continue operation.
Repeated Start
This bit indicates that a repeated start condition occurred
on the bus, but only when this interface was involved in
the original transfer.
Interrupt Status (ISR)
STS
5
0
BER
4
0
LRB/AD0
3
0
register, if the Two-Wire Serial
Interrupt Mask (IMR)
AAS
2
0
LAB
1
0
BB_N
0
0
6-7
3
2
1
0
7
6