MC68HC908QT2CPE Freescale, MC68HC908QT2CPE Datasheet - Page 45
MC68HC908QT2CPE
Manufacturer Part Number
MC68HC908QT2CPE
Description
Manufacturer
Freescale
Datasheet
1.MC68HC908QT2CPE.pdf
(184 pages)
Specifications of MC68HC908QT2CPE
Cpu Family
HC08
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
128Byte
# I/os (max)
6
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
4-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
8
Package Type
PDIP
Program Memory Type
Flash
Program Memory Size
1.5KB
Lead Free Status / RoHS Status
Compliant
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3.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the
analog circuitry before using ADC data after exiting stop mode.
3.6 Input/Output Signals
The ADC module has four channels that are shared with I/O port A.
ADC voltage in (ADCVIN) is the input voltage signal from one of the four ADC channels to the ADC
module.
3.7 Input/Output Registers
These I/O registers control and monitor ADC operation:
3.7.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and control register (ADSCR). When a
conversion is in process and the ADSCR is written, the current conversion data should be discarded to
prevent an incorrect reading.
COCO — Conversions Complete Bit
Freescale Semiconductor
•
•
•
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion.
COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It
always reads as a 0.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1)
ADC status and control register (ADSCR)
ADC data register (ADR)
ADC clock register (ADICLK)
Address: $003C
The write function of the COCO bit is reserved. When writing to the ADSCR
register, always have a 0 in the COCO bit position.
Reset:
Read:
Write:
COCO
Figure 3-3. ADC Status and Control Register (ADSCR)
Bit 7
R
R
0
= Reserved
MC68HC908QY/QT Family Data Sheet, Rev. 6
AIEN
6
0
ADCO
5
0
NOTE
CH4
4
1
CH3
3
1
CH2
2
1
CH1
1
1
Input/Output Signals
Bit 0
CH0
1
45
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