MC68HC908QT2CPE Freescale, MC68HC908QT2CPE Datasheet - Page 131

• Manufacturer Part Number: MC68HC908QT2CPE
• Manufacturer: Freescale

Specifications of MC68HC908QT2CPE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 6
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 4-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Package Type: PDIP
• Program Memory Type: Flash
• Program Memory Size: 1.5KB
• Lead Free Status / RoHS Status: Compliant

ELSxB and ELSxA — Edge/Level Select Bits
TOVx — Toggle-On-Overflow Bit
Freescale Semiconductor
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see
Reset clears the MSxA bit.
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is
available as a general-purpose I/O pin.
the ELSxB and ELSxA bits.
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect Reset clears the TOVx bit.
1 = Initial output level low
0 = Initial output level high
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
MSxB
X
X
0
0
0
0
0
0
0
1
1
1
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
After initially enabling a TIM channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
MSxA
X
X
X
0
1
0
0
0
1
1
1
1
ELSxB
0
0
0
1
1
0
0
1
1
0
1
1
Table 14-3. Mode, Edge, and Level Selection
MC68HC908QY/QT Family Data Sheet, Rev. 6
ELSxA
0
0
1
0
1
0
1
0
1
1
0
1
Table 14-3
Output compare
Buffered output
buffered PWM
Output preset
Input capture
compare or
or PWM
Mode
NOTE
NOTE
NOTE
shows how ELSxB and ELSxA work. Reset clears
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
Configuration
Input/Output Registers
Table
14-3).
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