MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 919

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

PB[7:0]
PA[7:0]
Reset
Reset
Field
23.0.5.2
Read: Anytime.
Write: Anytime.
Field
23.0.5.3
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in
all other modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
7–0
7–0
W
W
R
R
DDRA7
Port A — Port A pins 7–0 are associated with address outputs ADDR15 through ADDR8 respectively inexpanded
modesWhen this port is not used for external addresses, these pins can be used as general purpose I/O. If the
data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register,
otherwise the buffered pin input state is read.
PB7
Port B — Port B pins 7–0 are associated with address outputs ADDR7 through ADDR1 respectively in expanded
modes. Pin 0 is associated with output ADDR0 in emulation modes and special test mode and with Upper Data
Select (UDS) in normal expanded mode. When this port is not used for external addresses, these pins can be
used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read
returns the value of the port register, otherwise the buffered pin input state is read.
7
0
7
0
Port B Data Register (PORTB)
Port A Data Direction Register (DDRA)
DDRA6
PB6
0
0
6
6
Figure 23-5. Port A Data Direction Register (DDRA)
Figure 23-4. Port B Data Register (PORTB)
Table 23-5. PORTB Field Descriptions
Table 23-4. PORTA Field Descriptions
DDRA5
PB5
5
0
5
0
DDRA4
PB4
0
0
4
4
Description
Description
DDRA3
PB3
3
0
3
0
DDRA2
PB2
0
0
2
2
DDRA1
PB1
1
0
1
0
DDRA0
PB0
0
0
0
0