MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 707

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

19.3.1.11.1 Debug Comparator Control Register (DBGXCTL)
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map
Read: Anytime
Write: Anytime when DBG not armed.
Freescale Semiconductor
(COMPB/D)
(COMPA/C)
0x0028
0x0028
Reset
Reset
Field
NDB
SZE
7
6
W
W
R
R
0x002A
0x002B
0x002C
0x002D
0x002E
0x0029
0x002F
SZE
Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the
associated comparator. This bit is ignored if the TAG bit in the same register is set.
0 Word/Byte access size is not used in comparison
1 Word/Byte access size is used in comparison
Not Data Bus Compare — The NDB bit controls whether the match occurs when the data bus matches the
comparator register value or when the data bus differs from the register value. Furthermore database bits can
be individually masked using the comparator data mask registers. This bit is only available for comparators A
and C. This bit is ignored if the TAG bit in the same register is set. This bit position has an SZ functionality for
comparators B and D.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
0
0
0
7
7
Figure 19-13. Debug Comparator Control Register (Comparators A and C)
Figure 19-14. Debug Comparator Control Register (Comparators B and D)
Unimplemented or Reserved
DATA HIGH COMPARATOR
DATA LOW COMPARATOR
NDB
SZ
0
0
6
6
ADDRESS MEDIUM
DATA HIGH MASK
DATA LOW MASK
ADDRESS HIGH
ADDRESS LOW
Table 19-27. DBGXCTL Field Descriptions
Table 19-26. Comparator Register Layout
MC9S12XDP512 Data Sheet, Rev. 2.21
TAG
TAG
0
0
5
5
BRK
BRK
0
0
4
4
Description
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
RW
RW
0
0
3
3
Chapter 19 S12X Debug (S12XDBGV2) Module
Comparator A and C only
Comparator A and C only
Comparator A and C only
Comparator A and C only
RWE
RWE
0
0
2
2
SRC
SRC
0
0
1
1
COMPE
COMPE
0
0
0
0
709