MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 613

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 17
Memory Mapping Control (S12XMMCV2)
17.1
This section describes the functionality of the module mapping control (MMC) sub-block of the S12X
platform. The block diagram of the MMC is shown in
The MMC module controls the multi-master priority accesses, the selection of internal resources and
external space. Internal buses including internal memories and peripherals are controlled in this module.
The local address space for each master is translated to a global memory space.
17.1.1
The main features of this block are:
17.1.2
This subsection lists and briefly describes all operating modes supported by the MMC.
17.1.2.1
1. Resources are also called targets.
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
•
Paging capability to support a global 8 Mbytes memory address space
Bus arbitration between the masters CPU, BDM, and XGATE
Simultaneous accesses to different resources
Resolution of target bus access collision
Access restriction control from masters to some targets (e.g., RAM write access protection for user
specified areas)
MCU operation mode control
MCU security control
Separate memory map schemes for each master CPU, BDM, and XGATE
ROM control bits to enable the on-chip FLASH or ROM selection
Port replacement registers access control
Generation of system reset when CPU accesses an unimplemented address (i.e., an address which
does not belong to any of the on-chip modules) in single-chip modes
Run mode
MMC is functional during normal run mode.
Introduction
Features
Modes of Operation
Power Saving Modes
MC9S12XDP512 Data Sheet, Rev. 2.21
1
(internal, external, and peripherals) (see
Figure
1-1.
Figure
1-1)
613