MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 179

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

5.3.2.13
The A/D conversion results are stored in 8 read-only result registers. The result data is formatted in the
result registers based on two criteria. First there is left and right justification; this selection is made using
the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using
the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left
justified format. Signed data selected for right justified format is ignored.
Read: Anytime
Write: Anytime in special mode, unimplemented in normal modes
5.3.2.13.1
5.3.2.13.2
Freescale Semiconductor
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
R
R
R
R
BIT 9 MSB
BIT 7 MSB
BIT 7 MSB
BIT 1
BIT 7
U
0
0
0
0
0
0
7
7
7
7
Figure 5-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
Figure 5-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
Figure 5-15. Left Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
Figure 5-16. Left Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
ATD Conversion Result Registers (ATDDRx)
Left Justified Result Data
Right Justified Result Data
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
BIT 8
BIT 6
BIT 0
BIT 6
BIT 6
U
6
0
6
0
6
0
0
0
6
0
BIT 7
BIT 5
BIT 5
BIT 5
0
0
0
0
0
0
0
0
5
5
5
5
MC9S12XDP512 Data Sheet, Rev. 2.21
BIT 6
BIT 4
BIT 4
BIT 4
0
0
0
0
0
0
0
0
4
4
4
4
BIT 5
BIT 3
BIT 3
BIT 3
0
0
0
0
0
0
0
0
3
3
3
3
Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
BIT 4
BIT 2
BIT 2
BIT 2
0
0
0
0
0
0
0
0
2
2
2
2
BIT 9 MSB
BIT 3
BIT 1
BIT 1
BIT 1
0
0
0
0
0
0
0
1
1
1
1
BIT 2
BIT 0
BIT 8
BIT 0
BIT 0
0
0
0
0
0
0
0
0
0
0
0
10-bit data
10-bit data
10-bit data
8-bit data
8-bit data
8-bit data
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