MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 372

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
8.3.2.5
The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be
center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See
Section 8.4.2.5, “Left Aligned Outputs”
description of the PWM output modes.
372
PCKB[2:0]
PCKA[2:0]
s
Reset
Field
6–4
2–0
W
R
CAE7
Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for channels 2, 3, 6, or
7. These three bits determine the rate of clock B, as shown in
Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for channels 0, 1, 4 or
5. These three bits determine the rate of clock A, as shown in
PWM Center Align Enable Register (PWMCAE)
0
7
PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock
pre-scale is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
CAE6
Figure 8-7. PWM Center Align Enable Register (PWMCAE)
PCKB2
PCKA2
0
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Table 8-4. PWMPRCLK Field Descriptions
Table 8-5. Clock B Prescaler Selects
Table 8-6. Clock A Prescaler Selects
MC9S12XDP512 Data Sheet, Rev. 2.21
CAE5
PCKB1
PCKA1
0
5
and
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Section 8.4.2.6, “Center Aligned Outputs”
CAE4
NOTE
PCKB0
0
PCKA0
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
CAE3
0
3
Value of Clock B
Value of Clock A
Table
Table
Bus clock / 128
Bus clock / 128
Bus clock / 16
Bus clock / 32
Bus clock / 16
Bus clock / 32
Bus clock / 64
Bus clock / 64
Bus clock / 2
Bus clock / 4
Bus clock / 8
Bus clock / 2
Bus clock / 4
Bus clock / 8
Bus clock
Bus clock
8-5.
8-6.
CAE2
0
2
Freescale Semiconductor
CAE1
for a more detailed
0
1
CAE0
0
0