MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 817

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
1
Write access not applicable for one or more register bits. Refer to
Descriptions”.
Address
0x026A
0x026B
0x026C
0x026D
0x026E
0x027A
0x027B
0x027C
0x027D
0x027E
0x0264
0x0265
0x0266
0x0267
0x0268
0x0269
0x026F
0x0270
0x0271
0x0272
0x0273
0x0274
0x0275
0x0276
0x0277
0x0278
0x0279
0x027F
Port H Pull Device Enable Register (PERH)
Port H Polarity Select Register (PPSH)
Port H Interrupt Enable Register (PIEH)
Port H Interrupt Flag Register (PIFH)
Port J Data Register (PTJ)
Port J Input Register (PTIJ)
Port J Data Direction Register (DDRJ)
Port J Reduced Drive Register (RDRJ)
Port J Pull Device Enable Register (PERJ)
Port J Polarity Select Register (PPSJ)
Port J Interrupt Enable Register (PIEJ)
Port J Interrupt Flag Register (PIFJ)
Reserved
Port AD0 Data Register 1 (PT1AD0)
Reserved
Port AD0 Data Direction Register 1 (DDR1AD0)
Reserved
Port AD0 Reduced Drive Register 1 (RDR1AD0)
Reserved
Port AD0 Pull Up Enable Register 1 (PER1AD0)
Port AD1 Data Register 0 (PT0AD1)
Port AD1 Data Register 1 (PT1AD1)
Port AD1 Data Direction Register 0 (DDR0AD1)
Port AD1 Data Direction Register 1 (DDR1AD1)
Port AD1 Reduced Drive Register 0 (RDR0AD1)
Port AD1 Reduced Drive Register 1 (RDR1AD1)
Port AD1 Pull Up Enable Register 0 (PER0AD1)
Port AD1 Pull Up Enable Register 1 (PER1AD1)
Table 22-2. PIM Memory Map (Sheet 3 of 3)
MC9S12XDP512 Data Sheet, Rev. 2.21
Use
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
Section 22.3.2, “Register
Read / Write
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Access
Read
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1
1
1
1
1
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