MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 642

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 17 Memory Mapping Control (S12XMMCV2)
17.4.4
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and
XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus
swapping operations. All internal and external resources are connected to specific target buses (see
Figure
17.4.4.1
The following rules apply when prioritizing accesses over master buses:
642
IO
•
•
1-26).
The CPU has priority over the BDM, unless the BDM access is stalled for more than 128 cycles.
In the later case the CPU will be stalled after finishing the current operation and the BDM will gain
access to the bus.
XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU
and BDM for its duration.
EBI
Chip Bus Control
Master Bus Prioritization
XEEPROM
XBus0
S12X
BDM
BDM
ROM/REG
MC9S12XDP512 Data Sheet, Rev. 2.21
Figure 17-26. S12X Architecture
MMC
XBus1
S12X
CPU
XRAM
XFLASH
XBus2
XGATE
RAM
XGATE
IPBI
Freescale Semiconductor
2 Kbyte Registers
P0
P1
P2
P3