LSISAS1068 LSI, LSISAS1068 Datasheet - Page 98

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

4-28
Table 4.4
Table 4.5
PCI Host Register Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Maximum Outstanding Split Transactions (Cont.)
Maximum Memory Read Count
Maximum Memory Read Byte Count
These bits indicate the maximum byte count the
LSISAS1068 uses when initiating a sequence with one of
the burst memory read commands.
the bit encodings for this field.
Reserved
This bit is reserved.
Data Parity Error Recovery Enable
The host device driver sets this bit to allow the
LSISAS1068 to attempt to recover from data parity
errors. If the user clears this bit and the LSISAS1068 is
operating in the PCI-X mode, the LSISAS1068 asserts
SERR/ whenever the Master Data Parity Error bit in the
PCI
Encoding
Encoding
Bits [6:4]
Bits [3:2]
0b100
0b101
0b110
0b111
Status
0b00
0b01
0b10
0b11
register is set.
Maximum Memory Read Byte Count
Maximum Outstanding
Split Transactions
Reserved
Reserved
1024
2048
512
12
16
8
Table 4.5
provides
[3:2]
1
0