LSISAS1068 LSI, LSISAS1068 Datasheet - Page 46

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

2.5
2.5.1
2-20
External Memory Interface
Memory Requirements
Figure 2.4
The external memory control block provides a direct slave interface
between the internal primary AHB bus and an external 32-bit memory
interface. This interface is for accessing external flash ROM and
NVSRAM devices. Because the LSISAS1068 uses a 32-bit multiplexed
address/data bus, designs using the LSISAS1068 do not require latches
or CPLD devices to construct memory addresses.
The memory requirements for the LSISAS1068 depend on the board
design and application. Several board design possibilities and their
respective memory requirements are presented as follows.
Functional Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Initiator
Target
SAS
SAS
System board implementation
–
–
Host Bus Adapter (HBA) implementation
–
Intelligent IOP implementation
SSP
If the system uses the firmware download boot procedure, then
the LSISAS1068 may require a PBSRAM depending on system
implementation.
If the system does not use the firmware download boot
procedure, then the LSISAS1068 requires only a flash ROM.
The LSISAS1068 requires only a flash ROM.
SSP, STP, and SMP Protocol Usage
Initiator
Target
SMP
SMP
SMP
Initiator
Target
SATA
SAS
SATA
Expander
Initiator
Target
SAS
SATA
SAS
STP
SATA