LSISAS1068 LSI, LSISAS1068 Datasheet - Page 43

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

2.3.6
2.4
SAS Functional Description
Power Management
specification. The LSISAS1068 implements its own MSI and MSI-X
register sets. The MSI functionality is managed through the MSI register
set, and the MSI-X functionality is managed through the MSI-X register
set. The PCI specification prohibits system software from simultaneously
enabling MSI and MSI-X.
The
interrupt to the host processor by selectively masking reply interrupts and
system doorbell interrupts. This register masks both pin-based and MSI-
based interrupts.
The LSISAS1068 complies with the PCI Power Management Interface
Specification, Revision 1.2, and the PC2001 System Design Guide. The
LSISAS1068 supports the D0, D1, D2, D3
D0 is the maximum power state, and D3 is the minimum power state.
Power State D3 is further categorized as D3
device off places it in the D3
The LSISAS1068 provides eight SAS/SATA phys. Each phy can form one
side of the physical link in a connection with a phy on a different
SAS/SATA device. The physical link contains four wires that form two
differential signal pairs. One differential pair transmits signals, while the
other differential pair receives signals. Both differential pairs operate
simultaneously, and allow concurrent data transmission in both the
receive and the transmit directions.
attached with a physical link.
SAS Functional Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Host Interrupt Mask
register also prevents the assertion of a PCI
cold
Power State.
Figure 2.2
hot
hot
, and D3
shows two phys that are
or D3
cold
cold
. Powering the
power states.
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