LSISAS1068 LSI, LSISAS1068 Datasheet - Page 32

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LSISAS1068

Manufacturer Part Number
LSISAS1068
Description
Manufacturer
LSI
Datasheet

Specifications of LSISAS1068

Lead Free Status / RoHS Status
Not Compliant

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2.1.1.8
2.1.1.9
2.1.1.10
2.1.2
2.1.2.1
2-6
Quad Port
Inter-IC (I
SIO A and SIO B Interface
UART
Transport Module
The LSISAS1068 contains an Inter-IC (I
with peripherals. This interface is also referred to as an industry standard
2-wire interface (ISTWI). The I
slave on the bus and sustains data rates up to 400 Kbits/s. The I
accomplishes byte-wise bidirectional data transfers by using either an
interrupt or a polling handshake at the completion of each byte. The style
and operation of this interface closely follows the defacto standard for a
two-wire serial interface chip. The I
performs bus-specific sequences.
The SIO interface enables the user to control LED pattern generation,
device information, and general purpose data. There is one SIO module
for each Quad Port module. SIO A controls of the LEDs in Quad Port
Module 0. SIO B controls the LEDs in Quad Port Module 1.
The SIO_DOUT signals transmit output data and SIO_IN signals receive
data. The SIO module generates a pulse on the SIO_END signal when
transmitting the last valid data bit. The SIO interface is compliant to the
SFF-8485 Serial GPIO (SGPIO) Bus specification.
The UART provides test and debug access to the LSISAS1068.
The Quad Port modules in the LSISAS1068 implement the SSP, SMP,
and STP/SATA protocols, and manage the eight SAS/SATA phys. Each
Quad Port module supports four SAS/SATA phys. The following
subsections describe the Quad Port modules. Refer to
Functional Description,”
SAS ports.
The transport modules transmit frames to and from the port layer and
implement the STP, SSP, and SMP protocols. Each Quad Port module
Functional Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
2
C) Interface
for an operational description of the LSISAS1068
2
C block operates as either a master or a
2
C block controls all bus timing and
2
C) interface that communicates
Section 2.4, “SAS
2
C block

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