LSISAS1068 LSI, LSISAS1068 Datasheet - Page 34

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LSISAS1068

Manufacturer Part Number
LSISAS1068
Description
Manufacturer
LSI
Datasheet

Specifications of LSISAS1068

Lead Free Status / RoHS Status
Not Compliant

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2.1.3
2.2
2-8
Fusion-MPT Architecture Overview
Context RAM
The context RAM is a memory that is shared between the host interface
module and the quad port modules. The context RAM contains the
message frames, the FIFOs, and a portion of the firmware.
The Fusion-MPT architecture provides two I/O methods for the host
system to communicate with the IOP: the system interface doorbell and
the message queues.
The system interface doorbell is a simple message passing mechanism
that allows the PCI host system and IOP to exchange single 32-bit
Dword messages. When the host system writes to the doorbell, the
LSISAS1068 hardware generates a maskable interrupt to the IOP, which
can then read the doorbell value and take the appropriate action. When
the IOP writes a value to the doorbell, the LSISAS1068 hardware
generates a maskable interrupt to the host system. The host system can
then read the doorbell value and take the appropriate action.
There are two, 32-bit message queues: the request message queue and
the reply message queue. The host uses the request queue to request
an action by the LSISAS1068, and the LSISAS1068 uses the reply
queue to return status information to the host. The request message
queue consists of the request post FIFO. The reply message queue
consists of both the reply post FIFO and the reply free FIFO. The context
RAM contains the message queues. The Fusion-MPT architecture also
provides a High Priority Request FIFO to provide high priority request
free messages to the host on reads and to accept high priority request
post messages from the host on writes.
Communication using the message queues occurs through request
messages and reply messages. Request message frame descriptors are
pointers to the request message frames and are passed through the
request post FIFO. The request message frame data structure is up to
128 bytes in length and includes a message header and a payload. The
header uniquely identifies the message. The payload contains
information that is specific to the request. Reply message frame
descriptors have one of two formats and are passed through the reply
Functional Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.

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