LSISAS1068 LSI, LSISAS1068 Datasheet - Page 63

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

3.9
Table 3.13
Signal Name
TST_RST/
REFCLK_B
MODE[5:0]
GPIO[3:0]
FAULT_LED[7:0]/
ACTIVE_LED[7:0]/ G1, J3, J4, J6,
HB_LED/
FSELA
Configuration and General Purpose Signals
Configuration and General Purpose Signals
BGA Position Type Description
F6
B13
G6, F4, D2,
G4, D1, E2
P3, R1, P4, P5 I/O
K2, K1, J1, L4,
K3, K4, H1, H2
H3, F1, H4, H6
M5
E3
Table 3.13
Configuration and General Purpose Signals
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
describes the configuration and general purpose signals.
I
I
I
O
O
O
I
Asserting the Test Reset signal forces the chip into a
Power-On-Reset state. This signal must be supplied by a
power-on reset circuit on the board.
This pin provides the ARM reference clock.
The Mode Select bus defines the operational and test
modes for the chip. For normal operation, pull these signals
to 0b000000.
These pins provide General Purpose Input/Output signals.
These pins have internal pull-ups and default to input mode
upon device reset.
The active LOW Fault LED signals are nominally configured
to indicate a SAS link fault for each respective phy.
The active LOW Activity LED signals are nominally
configured to indicate SAS link activity.
The active LOW Heart Beat LED signal is nominally
configured to intermittently assert, which indicates that the
IOP is operational.
The Frequency Select signal supports clocking
configuration options for internal clocks. This signal is
reserved for diagnostic purposes.
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