LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 7

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

TQFP/STQFP
PIN #
86
97
87
98
88
99
Data Set
Ready 1
Data Set
Ready 2
Request to Send 1
Request to Send 2
Clear to
Send 1
Clear to
Send 2
NAME
nDSR1
nDSR2
nRTS1
nRTS2
nCTS1
nCTS2
SYMBOL
FUNCTION
TYPE PER
BUFFER
O6
O6
7
I
I
I
I
1
Active low Data Set Ready inputs for the
serial port. Handshake signal which
notifies the UART that the modem is ready
to establish the communication link. The
CPU can monitor the status of nDSR
signal by reading bit 5 of Modem Status
Register (MSR).
change from low to high after the last MSR
read will set MSR bit 1 to a 1. If bit 3 of
Interrupt Enable Register is set, the
interrupt
changes state.
Note: Bit 5 of MSR is the complement of
nDSR.
Active low Request to Send outputs for the
Serial Port. Handshake output signal
notifies modem that the UART is ready to
transmit data.
programmed by writing to bit 1 of the
Modem Control Register (MCR).
hardware reset will reset the nRTS signal
to inactive mode (high). nRTS is forced
inactive during loop mode operation.
Active low Clear to Send inputs for the
serial port.
notifies the UART that the modem is ready
to receive data. The CPU can monitor the
status of nCTS signal by reading bit 4 of
Modem Status Register (MSR). A nCTS
signal state change from low to high after
the last MSR read will set MSR bit 0 to a 1.
If bit 3 of the Interrupt Enable Register is
set, the interrupt is generated when nCTS
changes state. The nCTS signal has no
effect on the transmitter.
Note: Bit 4 of MSR is the complement of
nCTS.
is
DESCRIPTION
generated
Handshake signal which
This signal can be
A nDSR signal state
when
nDSR
The