LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 28

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy
controller clock and data separator circuits will be turned off. The controller will come out of manual low
power mode after a software reset or access to the Data Register or Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self
clearing.
Note:
Configuration section (CR14).
Drive Rate Table (Recommended)
Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.
The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located in the
DRT1
DRIVE RATE
0
0
0
0
0
0
0
0
1
1
1
1
DRT0
0
0
0
0
1
1
1
1
0
0
0
0
SEL1
DATA RATE
1
0
0
1
1
0
0
1
1
0
0
1
PRECOMP
Table 7 – Precompensation Delays
432
111
001
010
011
100
101
110
000
00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
SEL0
1
0
1
0
1
0
1
0
1
0
1
0
Table 8 – Data Rates
1Meg
1Meg
1Meg
2Meg
MFM
500
300
250
500
500
250
500
250
DATA RATE
PRECOMPENSATION
<2Mbps
Default
125.00
166.67
208.33
250.00
28
41.67
83.34
0.00
DELAY (nsec)
Default: See Table 10
250
150
125
250
250
125
250
125
FM
---
---
---
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Default
2Mbps
104.2
20.8
41.7
62.5
83.3
125
0
DENSEL
1
1
0
0
1
1
0
0
1
1
0
0
DRATE(1)
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0