LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 170

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

Register Block
Config. Port
Note 2: The Configuration Port is at either 0x02E or 0x04E (for SYSOPT=0 or SYSOPT=1) at power
Note A. Logical Device IRQ and DMA Operation
1.
disabled by a register bit in that logical block, the IRQ and/or DMA channel is disabled. This is in addition
to the IRQ and DMA channel disabled by the Configuration Registers (active bit or address not valid).
a.
b.
c.
LOGICAL
Runtime
DEVICE
up and can be relocated via CR12 and CR13.
IRQ and DMA Enable and Disable: Any time the IRQ or DMA channel for a logical block is
FDC: For the following cases, the IRQ and DMA channel used by the FDC are disabled.
Digital Output Register (Base+2) bit D3 (DMAEN) set to "0".
The FDC is in power down (disabled).
Serial Ports:
Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port
interruptis disabled.
Disabling DMA Enable bit, disables DMA for UART2. Refer to the IrCC specification.
Parallel Port:
I.
ii.
REGISTER
0x12, 0x13
(Note 2)
(FROM ECR REGISTER)
INDEX
SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is
disabled.
ECP Mode:
(1)
(2)
000
001
010
011
100
101
110
111
0x30
MODE
(DMA) dmaEn from ecr register. See table below.
IRQ - See table below.
on 16-byte boundaries
On 2-byte boundaries
PRINTER
[0x0100:0x07FE]
CONFIG
[0x0100:0x0FF0]
TEST
FIFO
ECP
RES
SPP
EPP
BASE I/O
(Note 1)
RANGE
170
CONTROLLED BY
IRQE
IRQE
IRQE
IRQE
IRQE
IRQ
(on)
(on)
(on)
+00 : PME_STS
.
.
.
+0F : GP4
(See Table 52 in the Runtime Registers
section for Full List)
See Configuration Registers in Table 55.
They are accessed through the index and
DATA ports located at the Configuration
Port address and the Configuration Port
address +1 respectively.
CONTROLLED BY
BASE OFFSETS
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
FIXED
DMA