LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 120

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LPC47N227TQFP

Manufacturer Part Number
LPC47N227TQFP
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LPC47N227TQFP

Lead Free Status / RoHS Status
Not Compliant

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Note 1: The signal “ANY IRQ CHANGE/DRQ ASSERTION” is the same as “CHANGE/ASSERTION” in
Note 2: The LPC47N227 continually monitors the state of nCLKRUN to maintain the PCI Clock until an
SIRQ_CLKRUN_EN
ANY IRQ CHANGE/
DRQ ASSERTION
Table 47.
active “ANY IRQ CHANGE/DRQ ASSERTION” condition has been transferred to the host in a
SER_IRQ/DMA cycle. For example, if “ANY IRQ CHANGE/DRQ ASSERTION” is asserted
before nCLKRUN is de-asserted (not shown in FIGURE 4), the LPC47N227 must assert
nCLKRUN as needed until the SER_IRQ/DMA cycle has completed.
nCLKRUN
PCI_CLK
1,2
FIGURE 4 – CLOCK START ILLUSTRATION
2 CLKS MIN.
120
DRIVEN BY
LPC47N227
nCLKRUN
LPC47N227
STOPS
DRIVING
nCLKRUN

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