LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 147

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

CR08
Register CR08 is reserved. The default value of this register after power up is 00H.
CR09
CR09 can only be accessed in the configuration state and after the CSR has been initialized to 09H.
CR09 is a test control register and all bits must be treated as Reserved. Note: all test modes are
reserved for SMSC use. Activating test mode registers may produce undesired results.
CR0A
CR0A can only be accessed in the configuration state and after the CSR has been initialized to 0AH.
CR0A defines the FIFO threshold for the ECP mode parallel port. Bits [5:4] are Reserved. Reserved
Bits cannot be written and return 0 when read. Bits [7:6] are the IR OUTPUT MUX bits and are reset to
the default state by a POR and a hardware reset.
BIT NO.
BIT NO.
7
0
1
2
3
4
5
6
7
Floppy Disk
Enable
Type: R/W
BIT NAME
Type: R/W
BIT NAME
Test 24
Test 25
Test 26
Test 27
Test 28
Test 29
Test 30
Test 31
Auto Power Management and Boot Drive Select
This bit controls the AUTOPOWER DOWN feature of the Floppy
Disk. The function is:
0 = Auto powerdown disabled (default)
1 = Auto powerdown enabled
This bit is reset to the default state by POR or a hardware reset.
Table 65 – CR09
Test 4
147
RESERVED FOR SMSC USE
Bits[7:4] = 0000 on HARD RESET
DESCRIPTION
DESCRIPTION
Default: 0x00 on VCC POR;
Default: 0x00 on VCC POR