LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 127

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

SYSTEM MANAGEMENT INTERRUPT (SMI)
The LPC47N227 implements a “group” nIO_SMI output pin. The System Management Interrupt is a
non-maskable interrupt with the highest priority level used for OS transparent power management. The
nSMI group interrupt output consists of the enabled interrupts from Super I/O Device Interrupts
(Parallel Port, Serial Port 1 and 2 and FDC) and many of the GPIOs pins. The GP12/nIO_SMI pin,
when selected for the nIO_SMI function, can be programmed to be active high or active low via bit 2 in
the GPIO Polarity Register 1 (CR32). The nIO_SMI pin function defaults to active low. The output
buffer type of the pin can be programmed to be open-drain or push-pull via GPIO Output Type Register
(CR39).
The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 and 2. The
nSMI output is then enabled onto the nIO_SMI output pin via bit[7] in the SMI Enable Register 2. The
SMI output can also be enabled onto the serial IRQ stream (IRQ2) via Bit[6] in the SMI Enable Register
2.
SMI Registers
The SMI event bits for the GPIOs events are located in the SMI status and Enable registers 1 and 2.
The polarity of the edge used to set the status bit and generate an SMI is controlled by the GPIO
Polarity Registers located in the Configuration section. For non-inverted polarity (default) the status bit
is set on the low-to-high edge. Status bits for the GPIOs are cleared on a write of ‘1’.
The SMI logic for the GPIO events is implemented such that the output of the status bit for each event
is combined with the corresponding enable bit in order to generate an SMI.
The SMI event bits for the super I/O devices are located in the SMI status and enable register 1 and 2.
All of these status bits are cleared at the source; these status bits are not cleared by a write of ‘1’. The
SMI logic for these events is implemented such that each event is directly combined with the
corresponding enable bit in order to generate an SMI.
See the “Runtime Registers” section for the definition of the SMI status and enable registers.
127