LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 116

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

The SER_IRQ data frame supports IRQ2 from a logical device on Period 3, which can be used for the
System Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the
SMI via the SMI Enable Register.
configure any logical devices as using IRQ2.
SER_IRQ Period 14 is used to transfer IRQ13. Logical devices FDC, Parallel Port, Serial Port 1, Serial
Port 2 have IRQ13 as a choice for their primary interrupt.
The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2 and onto
the nIO_SMI pin via bit 7 of the SMI Enable Register 2.
Stop Cycle Control
Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by
initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is
indicated when the SER_IRQ is low for two or three clocks. If the Stop Frame’s low time is two clocks
then the next SER_IRQ Cycle’s sampled mode is the Quiet mode; and any SER_IRQ device may
initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s pulse. If the
Stop Frame’s low time is three clocks then the next SER_IRQ Cycle’s sampled mode is the Continuos
mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the
rising edge of the Stop Frame’s pulse.
Latency
Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host
supported IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84#S with a 25MHz PCI Bus or
2.88uS with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for
IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous
buses, and approximately double for asynchronous buses.
SER_IRQ PERIOD
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
SER_IRQ Sampling Periods
SIGNAL SAMPLED
Likewise, when using Period 3 for nSMI the user should not
nIO_SMI/IRQ2
Not Used
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
116
# OF CLOCKS PAST START
11
14
17
20
23
26
29
32
35
38
41
44
47
2
5
8