LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 15

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

The GPIOs that are used for PME wakeup inputs
are
These GPIOs function as follows:
!"
All GPIOs listed above are for PME wakeup as a
GPIO function (or alternate function).
See the Table in the GPIO section for more
information.
The following list summarizes the blocks,
registers and pins that are powered by VTR.
!"
!"
!"
push-pull or open drain under VTR power
(VCC=0), are powered by VTR. This means
they will, at a minimum, source their
specified current from VTR even when VCC
is present. This applies to the nIO_PME pin
only.
Buffers are powered by VCC, but in the
absence
protected (they do not impose a load on any
external VTR powered circuitry). They are
wakeup compatible as inputs under VTR
power. These pins have input buffers into
the wakeup logic that are powered by VTR.
PME interface block
Runtime register block (includes all PME,
SMI, GP data registers)
Pins for PME Wakeup:
GP10-GP17,
- GPIOs
GP30-GP37) as input
- nIO_PME as input
of
(GP10-GP17,
VCC
GP20-GP24, GP30-GP37.
they
are
GP20-GP24,
backdrive
15
Maximum Current Values
See the “Operational Description” section for the
maximum current values.
The maximum VTR current, I
outputs open (not loaded), and all inputs in a
fixed state (i.e., 0V or 3.3V). The total maximum
current for the part is the unloaded value PLUS
the maximum current sourced by the pin that is
driven by VTR. The pin that is powered by VTR
(as output) is nIO_PME. This pin, if configured
as a push-pull output, will source a minimum of
6mA at 2.4V when driving.
The maximum VCC current, I
outputs open (not loaded), and all inputs in a
fixed state (i.e., 0V or 3.3V).
Power Management Events (PME/SCI)
The LPC47N227 offers support for Power
Management Events (PMEs), also referred to as
System Control Interrupt (SCI) events. The
terms PME and SCI are used synonymously
throughout this document to refer to the
indication of an event to the chipset via the
assertion of the nIO_PME output signal on pin
17.
connect the nIO_PME pin to PCI PME pins.
See the “PME Support” section. Do not
TR
CC
, is given with all
, is given with all