RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 93

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

3.6.22
Intel
®
82845 MCH for SDR Datasheet
R
ERRCMD1—Error Command Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
Bit
7:1
Bit
0
0
Reserved.
SERR on Receiving Target Abort (SERTA).
0 = MCH does not assert an SERR message upon receipt of a target abort on AGP. SERR
1 = MCH generates an SERR message over the hub interface when a target abort is received on
Parity Error Response Enable (PER_EN)—R/W. Controls MCH’s response to data phase parity
errors on AGP.
0 = Address and data parity errors on AGP are not reported via the MCH hub interface SERR#
1 = The G_PERR# signal is not implemented by the MCH. However, when this bit is set to 1,
messaging mechanism. Other types of error conditions can still be signaled via SERR#
messaging independent of this bit’s state.
address and data parity errors detected on AGP are reported via hub interface SERR#
messaging mechanism, if further enabled by SERRE1.
messaging for Device 1 is globally enabled in the PCICMD1 register.
AGP.
40h
00h
R/W
8 bits
Descriptions
Description
Register Description
93