RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 46

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.5.3
46
PCICMD—PCI Command Register (Device 0)
Address Offset:
Default:
Access:
Size
Since MCH Device 0 does not physically reside on PCI0, many of the bits are not implemented.
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Reserved.
Fast Back-to-Back—RO. Not implemented; Hardwired to 0. This bit controls whether or not the
master can do fast back-to-back write. Since device 0 is strictly a target this bit is not
implemented.
SERR Enable (SERRE)—R/W. This bit is a global enable bit for Device 0 SERR messaging.
The MCH does not have an SERR# signal. The MCH communicates the SERR# condition by
sending a SERR message to the ICH2.
0 = Disable. SERR message is not generated by the MCH for Device 0.
1 = Enable. The MCH is enabled to generate SERR messages over the hub interface for
NOTE: This bit only controls SERR message for the Device 0. Device 1 has its own SERRE
Address/Data Stepping—RO. Not implemented; Hardwired to 0.
Parity Error Enable (PERRE)—RO. Not implemented; Hardwired to 0.The PERR# signal is not
implemented by the MCH.
VGA Palette Snoop—RO. Not implemented; Hardwired to 0.
Memory Write and Invalidate Enable(MWIE)—RO. Not implemented; Hardwired to 0.
Special Cycle Enable(SCE)—RO. Not implemented; Hardwired to 0.
Bus Master Enable (BME)—RO. Hardwired to 1. The MCH is always enabled as a master on
the hub interface.
Memory Access Enable (MAE)—RO. Not implemented; Hardwired to 1. The MCH always
allows access to system memory.
I/O Access Enable (IOAE)—RO. Not implemented; Hardwired to 0.
specific Device 0 error conditions that are individually enabled in the ERRCMD Register. The
error status is reported in the ERRSTS and PCISTS registers.
bits to control error reporting for error conditions occurring on their respective devices.
04–05h
0006h
R/W, RO
16 bits
Descriptions
Intel
®
82845 MCH for SDR Datasheet
R