RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 37

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

3.4.1
Intel
®
82845 MCH for SDR Datasheet
Note: Since there are multiple clock signals assigned to each row of a DIMM, it is important to clarify
R
DRAMWIDTH—DRAM Width Register
Address Offset:
Default Value:
Access:
Size:
This register determines the width of SDRAM devices populated in each row of memory.
exactly which row width field affects which clock signal.
7:6
Bit
5
4
3
2
1
0
Row Parameters
Reserved.
Row 5 Width. Width of devices in Row 5
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
Row 4 Width. Width of devices in Row 4
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
Row 3 Width. Width of devices in Row 3
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
Row 2 Width. Width of devices in Row 2
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
Row 1 Width. Width of devices in Row 1
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
Row 0 Width. Width of devices in Row 0
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
0
1
2
3
4
5
SDR Clocks Affected
SCK[8], SCK[10]
SCK[9], SCK[11]
SCK[0], SCK[2]
SCK[1], SCK[3]
SCK[4], SCK[6]
SCK[5], SCK[7]
2Ch
00h
R/W
8 bits
Descriptions
Register Description
37