RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 77

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82845 MCH for SDR Datasheet
R
Bit
4
3
2
1
0
SERR on AGP Access Outside of Graphics Aperture (OOGF_SERR).
0 = Disable.
1 = Enable. Generation of the hub interface SERR message is enabled when an AGP access
SERR on Invalid AGP Access (IAAF_SERR).
0 = Disable.
1 = Generation of the hub interface SERR message is enabled when an AGP access occurs to
SERR on Invalid Translation Table Entry (ITTEF_SERR).
0 = Disable.
1 = Enable. Generation of the hub interface SERR message is enabled when an invalid
SERR Multiple-Bit DRAM ECC Error (DMERR_SERR).
0 = Disable. For systems not supporting ECC, this bit must be disabled.
1 = Enable. Generation of the hub interface SERR message is enabled when the MCH system
SERR on Single-bit ECC Error (DSERR).
0 = Disable. For systems that do not support ECC, this bit must be disabled.
1 = Enable. Generation of the hub interface SERR message is enabled when the MCH system
occurs to an address outside of the graphics aperture.
an address outside of the graphics aperture and either to the 640 KB – 1 MB range or above
the top of memory.
translation table entry was returned in response to an AGP access to the graphics aperture.
memory controller detects a multiple-bit error.
memory controller detects a single bit error.
Description
Register Description
77