RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 49

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

3.5.8
3.5.9
Intel
®
82845 MCH for SDR Datasheet
R
MLT—Master Latency Timer Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
The hub interface does not comprehend the concept of Master Latency Timer. Therefore, this
register is not implemented.
HDR—Header Type Register (Device 0)
Address Offset:
Default:
Access:
Size:
This register identifies the header layout of the configuration space.
Bit
7:0
Bit
7:0
Hardwired to 00h. Writes have no effect.
Hardwired to 00h. Writes have no effect.
0Dh
00h
RO
8 bits
0Eh
00h
RO
8 bits
Description
Description
Register Description
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